DSP data memory layouts optimized for intermediate address pointer updates

Dedicated address generation units (AGUs) in modern digital signal processors (DSPs) support data memory access by indirect addressing with subsequent address pointer modification in parallel to other machine operations. In this paper, we present an integrated data memory layout and address register assignment optimization procedure. This technique allows to reduce both execution time and code size of DSP programs. Our generic AGU model is consistent with AGUs of contemporary fixed-point DSPs. It captures important addressing capabilities of DSPs such as linear addressing, module addressing and auto-modifying within a given auto-modify range. There is no address computation overhead if the next address is within the auto-modify range. We exploit multiple address pointer update opportunities between data memory accesses. Experimental results demonstrate that the proposed technique significantly outperforms existing optimization strategies