Modeling and analysis of PSRR in analog PWM class D amplifiers

In this paper, we propose and derive a linear model of a closed-loop PWM class D amplifier (CDA) to model its power supply rejection ratio (PSRR). On the basis of the proposed model, we derive a simple expression that depicts the effects of 3 critical parameters on PSRR: the gain of the integrator, the gain of the PWM stage and the feedback factor. We recommend, from a practical viewpoint, that the first and third parameters be increased if higher PSRR is desired. We validate our model and analysis on the basis of HSPICE simulations and on experimental measurements. Our model and analysis are useful as they provide insight to a CDA designer, in particular how various parameters may be varied/compromised to meet a given set of PSRR specifications