Debug support for embedded processor reuse

This research presents a test-bench implementation of a novel debug support system that targets the needs of hard real-time embedded systems. The solution provides over 70 percent combined program and data trace compression using a low complexity messaging framework and subtraction based differential compression. The test-bench is based on an open source multi-processor system-on-chip design, where novel debug support has been attached through defined interfaces and close integration of the debug adapter with the processor cores. Synthesis to an FPGA platform shows that the approach of using core adapters to implement debug support with a defined core generic interface is practical, and that the resulting circuitry is compact