Hierarchical exploration and selection of transistor-topologies for analog circuit design

This paper presents a method of design automation for analog circuits, focusing on topology generation and quick performance evaluation. First we describe a new mechanism to generate circuit topologies with hierarchical blocks, which are specialized by additional terminal information. The connection between blocks is in compliance with a set of synthesis rules, which are extracted from typical schematics in the literature. Fast symbolic analysis of linear performances is used to select appropriate topologies quickly. Finally, the selected topologies can be sized by an external sizing tool. Experimental results show the creativity and efficiency of our method