Architecture refinements by code refactoring of behavioral VHDL-AMS models

This paper presents an automatic structure synthesis technique by partitioning the system representation, which consists of interconnected analog and mixed-signal behavioral models coded in VHDL-AMS. The proposed model code refining methodology restructures, refines, and simplifies behavioral models by means of code transformations of given abstract models. The fundamental approach for these transforms is code refactoring - an approach taken from software engineering and adjusted to the requirements of analog circuit synthesis. Through code refactoring one improves the comprehensibility, expandability, and reusability of a behavioral block model and restructures the model such that subsequent circuit synthesis steps may produce adequate structural representations of the intended behavior. Application examples demonstrate the feasibility of this approach to architecture synthesis