Post-layout energy-delay analysis of parallel multipliers

This paper examines parallel multiplier architectures with respect to post-layout energy and delay. Our energy-delay analysis applied to several schemes takes into account the architectural as well as practical circuit implementation issues. Incorporating extracted 3D parasitic loads after layout, our analysis leads to a more realistic conclusion than previous work. A novel parallel-select Booth2 coding method is proposed to improve the performance of the multiplier. Our analysis concludes that the Booth2 method achieves better energy efficiency for large multipliers and for high speed, while the non-Booth method consumes less for small multipliers and longer latencies