Title :
A low-power clock frequency multiplier
Author :
Faisal, Md Ibrahim ; Bayoumi, Magdy ; Zhao, Peiyi
Author_Institution :
Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA
Abstract :
A low-power output feedback controlled frequency multiplier is proposed for delay locked loop (DLL) based clock synthesizers. It uses N voltage controlled delay lines (VCDL) to multiply the input clock frequency by a factor of N/2. This frequency multiplier is less susceptible to jitter-accumulation. The proposed circuit can operate at a substantially low supply voltage. Simulation results show that the proposed frequency multiplier dissipates about 27% to 36% less power than other similar circuits. In addition, the proposed circuit can be easily programmed for generating various output clock frequencies
Keywords :
clocks; delay lines; delay lock loops; frequency multipliers; low-power electronics; clock frequency generation; clock frequency multiplier; clock synthesizer; delay locked loop; voltage controlled delay lines; Circuit simulation; Clocks; Delay lines; Digital systems; Frequency conversion; Frequency synthesizers; Jitter; Power supplies; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692880
