• DocumentCode
    2535796
  • Title

    New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial

  • Author

    Chen, Zih-Heng ; Jing, Ming-Haw ; Chen, Jian-Hong ; Chang, Yaotsu

  • Author_Institution
    Dept. of Inf. Eng., I-Shou Univ.
  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    Recently, normal bases have been an appealing technique for hardware implementation in many applications, especially when finite fields are very large, such as the public key cryptosystems. In this article, a new viewpoint is introduced for performing the multiplication in the normal basis representation over binary field where the field defining irreducible polynomial is an all-one polynomial. The proposed multipliers carry out the normal basis multiplication by using extended polynomial basis multiplier to construct two architectures. These two classes of architectures are in bit-serial and bit-parallel which reduce the cost of space and time respectively
  • Keywords
    binary sequences; digital arithmetic; logic design; multiplying circuits; polynomials; public key cryptography; binary field; bit-parallel normal basis multipliers; bit-serial normal basis multipliers; cryptography; extended polynomial basis multiplier; finite fields; irreducible all-one polynomial; normal basis representation; Arithmetic; Code standards; Costs; Councils; Galois fields; Hardware; Mathematics; Polynomials; Public key cryptography; Reed-Solomon codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1692881
  • Filename
    1692881