DocumentCode :
2536019
Title :
Unified fully-pipelined VLSI implementations of two-dimensional discrete trigonometric transforms
Author :
Shie, Mon-Chau ; Wen-Hsien Fang ; Wu, Ming-Lu ; Lai, Feipei
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
1998
fDate :
24-27 Nov 1998
Firstpage :
623
Lastpage :
626
Abstract :
This paper describes a unified VLSI architecture which can efficiently realize some popular two-dimensional discrete trigonometric transforms (2-D DTT). The computation of the 2-D DTT is based on the row-column decomposition approach. However, in contrast to previous schemes, efficient and unrestricted Clenshaw´s recurrence formula along with the inherent symmetry of the trigonometric functions are adequately employed to render efficient recurrences for computing both of the row and column transforms. As such, the resulting VLSI architecture not only provides substantial hardware savings as compared with previous works, but it can also be applied to the 2-D DTT of arbitrary size. An input buffer along with a bidirectional circular shift matrix are addressed as well to enable the architecture to operate in a fully-pipelined manner
Keywords :
VLSI; digital signal processing chips; discrete transforms; pipeline arithmetic; 2D discrete trigonometric transforms; Clenshaw recurrence formula; bidirectional circular shift matrix; fully-pipelined VLSI implementations; input buffer; row-column decomposition approach; two-dimensional trigonometric transforms; unified VLSI architecture; Computer architecture; Computer science; Discrete Fourier transforms; Discrete cosine transforms; Discrete transforms; Face; Fourier transforms; Hardware; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location :
Chiangmai
Print_ISBN :
0-7803-5146-0
Type :
conf
DOI :
10.1109/APCCAS.1998.743897
Filename :
743897
Link To Document :
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