Multiplexing schemes for cost-effective fault-tolerance

Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a novel analysis of vN-MUX of 3-input majority gates (MAJ-3), using combinatorial arguments to exactly determine performance. We show that MAJ-3 vN-MUX performs very well when compared to other redundancy schemes, increasing the allowed device error probability by four orders of magnitude (for small redundancy factors). We describe in detail an extension, called MAJ-3 vN-MUX(N,k), that contributes up to four more orders of magnitude, by excluding superfluous restorative stages for very small redundancy factors. We also analytically determine the performance of MAJ-3 vN-MUX for large redundancy factors, finding that the maximum tolerable gate failure probability is 0.0197 (in contrast to 0.0107 for NAND-2 vN-MUX).