Integrating observability don´t cares in all-solution SAT solvers

All-solution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA industry in fields such as formal verification, circuit synthesis and automatic test pattern generation. Typically, these engines iteratively find each solution by calling a standard SAT solving procedure. Each solution is minimized using different post processing techniques and the problem is constrained to prevent recurring solutions. In this work, instead of applying post processing techniques, the objective is to minimize the size of the solution "on the fly" during the all-solution SAT solving process. This is achieved by allowing the solver to exploit the structural circuit observability don\´t cares (ODC) arising from the problem. The solver makes decisions such that the number of ODCs is maximized in each solution thus leading to an overall smaller number of iterations. Through extensive experiments, it is demonstrated that integrating ODC techniques within an all-solution SAT solver results in increased performance and more compact solutions