Self-sampled vernier delay line for built-in clock jitter measurement

Author

Cheng, Kuo-Hsing ; Huang, Chan-Wei ; Jiang, Shu-Yu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli

fYear

2006

fDate

21-24 May 2006

Lastpage

1594

Abstract

For high-speed analog and mixed signal circuits, on-chip clock jitter measurement has been a challenge in recent years. Circuit resolution, chip area, and frequency range are critical specification for built-in-test (BIT) circuit design. In order to fulfil these requirements, the self-sampled Vernier delay line (VDL) structure is proposed. Comparing with traditional VDL structure, there is no more jitter free sample clock used in this design. When the proposed circuit is designed in 14 ps circuit resolution, only 500mum*750mum chip area is used for 100 MHz to 400 MHz measurement range in TSMC 0.35mum CMOS process

Keywords

CMOS integrated circuits; built-in self test; clocks; delay lines; integrated circuit measurement; jitter; 0.35 micron; 100 to 400 MHz; 14 ps; 500 micron; 750 micron; CMOS process; built-in clock jitter measurement; built-in-test circuit design; chip area; circuit resolution; frequency range; high-speed analog circuits; mixed signal circuits; on-chip clock jitter measurement; self-sampled Vernier delay line; Circuits; Clocks; Delay effects; Delay lines; Electric variables measurement; Frequency; Semiconductor device measurement; Signal resolution; Time measurement; Timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692904

Filename

1692904