Title :
Design of multi-valued QMOS pre-decoder
Author :
Zhang, Hui ; Uemura, Tetsuya ; Mazumder, Pinaki ; Yang, Kyounghoon
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
In this paper, we have proposed two new four-valued pre-decoder circuits to drive address-stretchable multi-valued decoder frequently used in high-density semiconductor memories. Our designs are based on resonant tunnelling diode (RTD) having negative differential resistance (NDR) I-V characteristics due to quantum tunnelling through its meso-scopic double barrier structure defining the quantum well. Logic operation of our designs depends on the control of switching sequence of the QMOS based literal gates. We have demonstrated the functionality of our designs at clock frequency of 5 GHz. We have also analyzed the design flexibility of the literal gates according to the device parameters. Finally, we have compared the speed, power, and power delay product (PDP) performance of these two proposed designs.
Keywords :
DRAM chips; decoding; logic design; logic gates; mesoscopic systems; multivalued logic circuits; negative resistance devices; resonant tunnelling diodes; semiconductor quantum wells; 5 GHz; I-V characteristics; NDR; RTD; address-stretchable multivalued decoder; clock frequency; device parameters; four-valued predecoder circuits; literal gates; logic operation; mesoscopic double barrier structure; multivalued quantum MOS predecoder; negative differential resistance; power delay product; quantum tunnelling; quantum well; resonant tunnelling diode; semiconductor memory; switching control; Circuits; Clocks; Decoding; Frequency; Logic design; Logic devices; Power semiconductor switches; Resonant tunneling devices; Semiconductor diodes; Semiconductor memory;
Conference_Titel :
Nanotechnology, 2004. 4th IEEE Conference on
Print_ISBN :
0-7803-8536-5
DOI :
10.1109/NANO.2004.1392437
