DocumentCode
2536445
Title
Incremental system verification and synthesis of minimally restrictive behaviours
Author
Brandin, B. ; Malik, R. ; Dietrich, P.
Author_Institution
Dept. of Software & Eng., Siemens Corp. Res., Munchen, Germany
Volume
6
fYear
2000
fDate
2000
Firstpage
4056
Abstract
An incremental approach to system verification is proposed, for system behaviours and safety properties described by means of finite-string languages and finite-state automata. Properties are verified with respect to subsystems of the overall system, nevertheless allowing assertions to be made about the entire system satisfying such properties. The proposed approach considers satisfaction of properties, controllability, and synthesis as successive verification steps. Furthermore, it allows the incremental augmentation of the system to be verified: after each verification step, either the desired property is verified, or a counter example is obtained, which, together with heuristics, provides the basis for the augmentation of a given subsystem for the next verification step
Keywords
control system synthesis; controllability; discrete event systems; finite automata; formal verification; optimisation; control synthesis; controllability; discrete event systems; finite-state automata; finite-string languages; heuristics; incremental system verification; supervisory control; Automata; Automatic control; Control system synthesis; Control systems; Controllability; Counting circuits; Discrete event systems; Safety; Supervisory control;
fLanguage
English
Publisher
ieee
Conference_Titel
American Control Conference, 2000. Proceedings of the 2000
Conference_Location
Chicago, IL
ISSN
0743-1619
Print_ISBN
0-7803-5519-9
Type
conf
DOI
10.1109/ACC.2000.876984
Filename
876984
Link To Document