DocumentCode
2536467
Title
Novel automatic tuning system using PLL with switched capacitor circuit technique
Author
Takagi, Shigetaka ; Wada, Kazuyuki ; Fujii, Nobuo ; Yanagisawa, Takeshi
Author_Institution
Fac. of Eng., Tokyo Inst. of Technol., Japan
fYear
1998
fDate
24-27 Nov 1998
Firstpage
699
Lastpage
702
Abstract
This paper has proposed on-chip integration of an automatic tuning system for continuous-time filters using a switched-capacitor circuit and down-sampling techniques. The proposed system requires no external components and it is free of DC amplifier input-offset voltage and harmonics produced by the phase comparator. Its performance has been confirmed by computer simulations. An important property of an automatic tuning system is to keep its control signal appropriate. After the control signal converges at a desired value, operation of the system can be suspended. This will avoid noise produced by clock signals and save on power consumption. Therefore it is very effective to use the proposed system together with non-volatile analog memories
Keywords
circuit tuning; continuous time filters; integrating circuits; phase locked loops; signal sampling; switched capacitor networks; LDI integrator; PLL; SC integrator; active filters; automatic tuning system; continuous-time filters; down-sampling techniques; nonvolatile analog memories; switched capacitor circuit; Automatic control; Circuit optimization; Clocks; Computer simulation; Control systems; Phase locked loops; Power harmonic filters; Switched capacitor circuits; System-on-a-chip; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location
Chiangmai
Print_ISBN
0-7803-5146-0
Type
conf
DOI
10.1109/APCCAS.1998.743917
Filename
743917
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