• DocumentCode
    2536805
  • Title

    A 700uA, 405MHz fractional-N All digital frequency-locked loop for MICS band applications

  • Author

    Shashidharan, S. ; Khalil, W. ; Chakraborty, S. ; Kiaei, S. ; Copani, T. ; Bakkaloglu, B.

  • Author_Institution
    Electr., Energy & Comput. Eng., Arizona State Univ., Tempe, AZ, USA
  • fYear
    2010
  • fDate
    23-25 May 2010
  • Firstpage
    409
  • Lastpage
    412
  • Abstract
    An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based loop filter followed by a digital-intensive ΣΔ current-steering DAC and a first-order-hold filter. The ADFLL achieves 9.5Hz frequency resolution, spanning the ISM 400MHz-410MHz band. The worst-case near-integer spur of -55dBc and a phase noise of -83dBc/Hz at 300kHz offset is measured. The ADFLL is fabricated on a 0.18um CMOS process, occupying 0.14mm2 die area, with a quiescent current consumption of 700uA.
  • Keywords
    CMOS integrated circuits; biomedical communication; biomedical equipment; frequency locked loops; frequency shift keying; frequency synthesizers; prosthetics; ΣΔ phase accumulator; CMOS; MICS band applications; built-in FSK modulator; current 700 muA; digital IIR-based loop filter; digital-intensive ΣΔ current-steering DAC; feedback path; fractional-N all digital frequency-locked loop; frequency 300 kHz; frequency 405 MHz; frequency 9.5 Hz; frequency synthesizer; high resolution single-bit digital ΣΔ frequency discriminator; medical implants communication systems; reference path; size 0.18 mum; Digital filters; Feedback; Frequency locked loops; Frequency shift keying; Frequency synthesizers; Implants; Microwave integrated circuits; Noise measurement; Phase measurement; Phase noise; ΣΔ DACs; digital PLLs; type-I PLLs;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    1529-2517
  • Print_ISBN
    978-1-4244-6240-7
  • Type

    conf

  • DOI
    10.1109/RFIC.2010.5477249
  • Filename
    5477249