Power improvement for 65nm nMOSFET with high-tensile CESL and fast nonlinear behavior modeling

Author

Chiu, Chia-Sung ; Chen, Kun-Ming ; Huang, Guo-Wei ; Lin, Shu-Yu ; Chen, Bo-Yuan ; Hung, Cheng-Chou ; Huang, Sheng-Yi ; Fan, Cheng-Wen ; Tzeng, Chih-Yuh ; Chou, Sam

Author_Institution

Nat. Nano Device Labs., Hsinchu, Taiwan

fYear

2010

fDate

23-25 May 2010

Firstpage

589

Lastpage

592

Abstract

In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor was designed to work far from 50 ohms. By mean of this model, the accurate nonlinear behaviors of nMOSFET were obtained rapidly.

Keywords

MOSFET; power transistors; X-parameters measurement; contact etch stop layer; high-tensile CESL; nMOSFET; nonlinear behavior modeling; polyharmonic distortion model extraction; power gain Improvement; power transistor; size 65 nm; CMOS technology; Etching; MOSFET circuits; Nonlinear distortion; Performance analysis; Power amplifiers; Predictive models; Semiconductor device modeling; Strain control; Stress control; Contact etch stop layer (CESL); PHD; X-parameters; nMOSFET; stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE

Conference_Location

Anaheim, CA

ISSN

1529-2517

Print_ISBN

978-1-4244-6240-7

Type

conf

DOI

10.1109/RFIC.2010.5477258

Filename

5477258