Title :
A very high performance address BUS encoder
Author :
Parandeh-Afshar, H. ; Afzali-Kusha, A. ; Khakifirooz, A.
Author_Institution :
Sch. of Electr. & Comput. Eng., Tehran Univ.
Abstract :
This paper presents a very fast and low-power address bus encoder which is less dependent on address bus width. Its encoding scheme is the same as TO-XOR encoding method but its encoder and decoder architectures are much faster. Both the analytical analysis and the simulation results show that the delay of proposed architecture is about one third of delay of optimized TO-XOR encoder/decoder
Keywords :
decoding; delay systems; encoding; system buses; address bus encoder; architecture delay; decoder architecture; encoder architecture; encoding scheme; Analytical models; Central Processing Unit; Control systems; Decoding; Delay; Encoding; Laboratories; Nanoelectronics; Paper technology; Power dissipation;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692939
