Performance analysis of parallel frame synchronization scheme in SDH systems

Author

Obaidat, M.S. ; Teng, Jun

Author_Institution

Dept. of Comput. Sc, Monmouth Univ., West Long Branch, NJ, USA

fYear

1997

fDate

22-25 Sep 1997

Firstpage

456

Lastpage

461

Abstract

We analyze the performance of a new parallel frame synchronization system used for SDH networks. The performance is measured by using false synchronous probability P_FS, the average synchronous incoming time T_ASI, the average synchronous catching time T_ASC, and the average synchronization holding time T_ASH. Analysis indicates that the performance of our scheme is similar to that of the traditional approaches, or better under some condition. Furthermore, our scheme permits designers to use off-the-shelf integrated circuits to build SDH synchronization system

Keywords

cache storage; probability; synchronisation; synchronous digital hierarchy; SDH networks; SDH synchronization system; average synchronization holding time; average synchronous catching time; average synchronous incoming time; false synchronous probability; off-the-shelf integrated circuits; parallel frame synchronization; performance analysis; Circuits; Cities and towns; Computer science; Detectors; Educational institutions; Frequency selective surfaces; Leak detection; Payloads; Performance analysis; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Communications and Networks, 1997. Proceedings., Sixth International Conference on

Conference_Location

Las Vegas, NV

ISSN

1095-2055

Print_ISBN

0-8186-8186-1

Type

conf

DOI

10.1109/ICCCN.1997.623351

Filename

623351