Title :
A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS
Author :
Lee, Joonhee ; Kim, Jaewook ; Cho, SeongHwan
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
This paper presents a digital-intensive RF sampling receiver composed of a noise-canceling bandpass low-noise amplifier (LNA) and an RF analog-to-digital converter (ADC) for multi-band multi-mode wireless communication. The proposed LNA employs an on-chip transformer to combine the outputs of a common-gate and a common-source LNA to reduce the noise figure and enhance the linearity, while providing tunable bandpass filtering from 1.8 to 2.4-GHz. The RF ADC employs a time-based architecture that uses time-interleaved VCOs with 1st order noise shaping property, which benefits from enhanced time resolution of advanced CMOS process. A prototype chip implemented in 90 nm CMOS process has an area of 0.3 mm2 and achieves SNR of 50 dB for 1-MHz signal bandwidth at 1.8 to 2.4-GHz carrier frequency, while consuming 20 mW from 1.2 V supply.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; interference suppression; low noise amplifiers; radio receivers; transformers; ADC; CMOS; LNA; RF analog-to-digital converter; carrier frequency; digital-intensive RF sampling receiver; frequency 1.8 GHz to 2.4 GHz; multiband multimode wireless communication; noise-canceling bandpass low-noise amplifier; power 20 mW; voltage 1.2 V; Analog-digital conversion; Band pass filters; CMOS process; Filtering; Linearity; Low-noise amplifiers; Noise figure; Radio frequency; Sampling methods; Wireless communication; LNA; RF sampling receiver; direct RF sampling; on-chip transformer; time-based ADC; time-interleaved;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-6240-7
DOI :
10.1109/RFIC.2010.5477270