DocumentCode :
25380
Title :
SEU Hardened Flip-Flop Based on Dynamic Logic
Author :
SheXiao Xuan ; Li, Ning ; Tong, Junmin
Author_Institution :
Sch. of Microelectron., Fudan Univ., Shanghai, China
Volume :
60
Issue :
5
fYear :
2013
fDate :
Oct. 2013
Firstpage :
3932
Lastpage :
3936
Abstract :
A conventional master-slave flip-flop is very sensitive to particle strike that causes an SEU. When the clock is high, an SEU may upset the logic state of the master latch resulting in a faulty output of this flip-flop, and the erroneous value will also be locked in the slave latch when clock is low. When the clock is low, an SEU may also upset the logic state of the slave latch, resulting in a faulty output of this flip-flop. This paper presents an SEU hardened flip-flop that can mitigate SEU using an error detection circuit and a multiplexer. When the clock is high or low, an SEU in the master or slave latch of a flip-flop can be detected by the error detection circuit using dynamic logic. The multiplexer selects a correct output according to the error indication signal. The proposed flip-flop has small area, power and delay overheads and good radiation hardening capabilities.
Keywords :
detector circuits; flip-flops; multiplexing equipment; radiation hardening (electronics); SEU hardened flip-flop; delay overheads; dynamic logic; error detection circuit; error indication signal; logic state; master latch; master-slave flip-flop; multiplexer; radiation hardening capability; single event upset; slave latch; Circuit faults; Clocks; Delays; Latches; Logic gates; MOS devices; Single event upsets; Flip-flop; hardened by design; radiation effects; single event upset (SEU);
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2013.2281138
Filename :
6609083
Link To Document :
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