DocumentCode
2538332
Title
Design of STR level converters for SoCs using the multi-island dual-VDD design technique
Author
Wang, Jinn-Shyan ; Chang, Yu-Juey ; Yeh, Chingwei ; Chu, Yuan-Hua
Author_Institution
Dept. of Electr. Eng., National Chung-Cheng Univ., Chia-Yi
fYear
2006
fDate
21-24 May 2006
Lastpage
1976
Abstract
In a 0.13 mum design environment, we design two level converters to convert signals from 0.6V and 0.8V to 1.2V, respectively, to fulfill the needs of a multi-island dual-VDD CMOS SOC. Heuristic sizing guidelines are proposed to achieve better conversion speed and lower conversion energy for both level converters
Keywords
CMOS integrated circuits; convertors; integrated circuit design; system-on-chip; 0.13 micron; 0.6 to 1.2 V; CMOS system-on-chip; STR level converters; multiisland dual-VDD design; CMOS technology; Design methodology; Electricity supply industry; Energy consumption; Feedback circuits; Guidelines; Low voltage; MOS devices; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1692999
Filename
1692999
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