CMOS voltage-mode analog multiplier

Author

Boonchu, Boonchai ; Surakampontorn, Wanlop

Author_Institution

Mahanakorn Univ. of Technol., Bangkok

fYear

2006

fDate

21-24 May 2006

Abstract

This paper proposes a CMOS voltage-mode four-quadrant analog multiplier. It is based on a pair of diode-connected MOS transistor that is biased with a constant current source, and a CMOS voltage difference circuit. Simulation results shows that the linear range is plusmn400 mV with the linearity error of 0.8% and the harmonic distortion of 0.62%. The minus;3dB bandwidth of 30MHz is achieved at the power consumption of 1.26mW

Keywords

CMOS analogue integrated circuits; analogue multipliers; constant current sources; harmonic distortion; -400 to 400 mV; 1.26 mW; 30 MHz; CMOS voltage difference circuit; CMOS voltage-mode analog multiplier; MOS transistor; constant current source; harmonic distortion; CMOS technology; Circuit simulation; Communications technology; Diodes; Harmonic distortion; Linearity; MOSFETs; Threshold voltage; Transconductance; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693003

Filename

1693003

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2538410