Integrated charge sensitive amplifier with pole-zero cancellation circuit for high rates

Author

Grybos, Pawel ; Idzik, Marek ; Swientek, Krzysztof ; Maj, Piotr

Author_Institution

Fac. of Phys. & Appl. Comput. Sci., AGH Univ. of Sci. & Technol., Cracow

fYear

2006

fDate

21-24 May 2006

Lastpage

2000

Abstract

We report on design and preliminary measurements of integrated charge sensitive amplifier dedicated to work with asynchronous high rate input signals. In this paper, we discuss the trade-off between high rate operation of CSA and its noise, taking into account the negative effects of pile-up pulses in readout electronics. The key element in the presented fast CSA is a pole-zero cancellation circuit. The architecture of the PZC circuit implemented in 0.35 mum CMOS technology is discussed in detailed. The first tests of high rate operation of CSA with PZC circuit up to 2 MHz of input signals are reported

Keywords

CMOS analogue integrated circuits; amplifiers; analogue processing circuits; poles and zeros; readout electronics; 0.35 micron; 2 MHz; CMOS technology; asynchronous high rate input signals; integrated charge sensitive amplifier; pole-zero cancellation circuit; readout electronics; CMOS technology; Capacitive sensors; Feedback circuits; Integrated circuit technology; Noise generators; Pulse amplifiers; Pulse generation; Pulse shaping methods; Readout electronics; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693005

Filename

1693005