Title :
Modeling high k gate current from p-type Si inversion layers
Author :
Fan, Y.-Y. ; Mudanai, S. ; Qi, W. ; Lee, J.C. ; Tasch, A.F. ; Register, L.F. ; Banerjee, S.K.
Author_Institution :
Microelectron. Res. Center, Texas Univ., Austin, TX, USA
Abstract :
High permittivity (high k) materials are being considered as replacement for SiO/sub 2/ as the gate dielectric since the higher physical thickness can reduce the direct tunneling current while retaining the low equivalent oxide thickness (EOT) required by next-generation MOSFETs. An unavoidable silicate layer or an intentional buffer layer such as SiO/sub 2/ to improve interface properties is always found between the high k layer and silicon substrate. In this paper, we explore issues that need to be considered when modeling gate current in such high k gate stack structures. We have studied the gate current due to electron tunneling from the p-type Si inversion layer.
Keywords :
dielectric thin films; electric current; elemental semiconductors; interface states; interface structure; inversion layers; permittivity; semiconductor device models; silicon; tunnelling; MOSFETs; Si; SiO/sub 2/ gate dielectric replacement; SiO/sub 2/-Si; direct tunneling current; electron tunneling; equivalent oxide thickness; gate current; high k gate current modeling; high k gate stack structures; high k layer; high k materials; high permittivity materials; intentional buffer layer; interface properties; modeling; p-type Si inversion layer; p-type Si inversion layers; physical thickness; silicate layer; silicon substrate; Conducting materials; Dielectric materials; Dielectric substrates; Electrons; High K dielectric materials; High-K gate dielectrics; Poisson equations; Semiconductor process modeling; Temperature dependence; Tunneling;
Conference_Titel :
Device Research Conference, 2000. Conference Digest. 58th DRC
Conference_Location :
Denver, CO, USA
Print_ISBN :
0-7803-6472-4
DOI :
10.1109/DRC.2000.877090
