Design optimization of stacked gate oxides with easy evaluation of gate leakage in deep submicron MOSFET

As the gate oxide is scaled down to 2 nm and below in a deep submicron CMOS transistor, direct tunneling and surface roughness seriously degrade the device performance. Alternative high-k materials are then considered to replace silicon dioxide. To achieve better interface quality and improve short channel effects, an extremely thin buffer layer of lower-k has been found favorable between the high-k layer and the silicon substrate. This leads to stacked gate architectures. The evaluation, however, of the gate leakage through such a complex potential barrier becomes an issue. Although a tedious numerical method may be employed (Ricco and Azbel, 1984), it is not necessary for many cases where an approximate analytical solution can offer valuable insights into the leakage problem and quick assistance for design consideration. In this work, we propose a simple method to evaluate the tunneling current through a double barrier for the first time. Accordingly, we study the design optimization of the architectures.