Title :
A transistor-based clock jitter insensitive DAC architecture
Author :
Gerfers, Friedel ; Ortmanns, Maurits ; Schmitz, Philipp
Author_Institution :
Philips Semicond., Starnberg
Abstract :
A decaying pulse shape DAC architecture for continuous-time (CT) SigmaDelta modulators is introduced. The DAC reduces the clock jitter sensitivity while putting only moderate design constrains on the respective integrators. The impact of clock jitter on the entire SigmaDelta modulator is computed and verified by electrical and behavioral simulations. In order to illustrate also the low-power benefits, the required integrator gain-bandwidth is evaluated and the obtained results are compared with corresponding simulation results. The DAC is implemented in a 1.8V 0.18mum CMOS process operating at a sampling frequency of fS=200MHz. The effect of process corners, supply voltage and temperature (PVT) is illustrated. Finally, various design constrains are discussed
Keywords :
CMOS integrated circuits; continuous time systems; delta-sigma modulation; timing jitter; transistors; 0.18 micron; 1.8 V; 200 MHz; CMOS process; clock jitter; continuous-time SigmaDelta modulators; decaying pulse shape DAC architecture; integrator gain-bandwidth; CMOS process; Clocks; Computational modeling; Computer architecture; Frequency; Jitter; Pulse modulation; Pulse shaping methods; Sampling methods; Shape;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693010
