A discrete resizing and concurrent power combining structure for linear CMOS power amplifier

We propose a new method of power combining for a parallel-combining-transformer (PCT)-based CMOS linear power amplifier (PA). The power cell in parallel paths is divided into three sub-cells to implement device resizing for discrete power control. Concurrent power combining of sub-power-cells utilizes the maximum available transformer efficiency even at the low-power mode, boosting overall PA efficiency. When all sub-power-cells are enabled, the PA exploits output power of 30.7 dBm with PAE of 35.8%. Power back-offs of 6 dB and 12 dB are achieved by discretely turning off sub-cells, showing output power of 25 dBm and 19 dBm with PAE of 19.8% and 10.5%, respectively. With 802.11g WLAN modulated signal used for linearity test, the PA shows 21-dBm output power satisfying -25-dB EVM requirements consuming 560 mA from 3.3 V power supply.