Title :
Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry
Author :
Amamiya, Yasushi ; Suzuki, Yasuyuki ; Yamazaki, Zin ; Mamada, Masayuki ; Hida, Hikaru
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Ibaraki, Japan
Abstract :
We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology is capable of high-speed (>40 Gb/s) selector operation with a large clock phase margin (>200 deg) at a supply voltage as low as 1.3 V using bipolar-based devices that require a relatively large supply voltage. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110 Gb/s with a 1.8-V supply voltage.
Keywords :
CMOS logic circuits; III-V semiconductors; flip-flops; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; integrated circuit design; low-power electronics; multiplexing equipment; switched current circuits; 1 W; 1.8 V; 40 Gbits/s; CMOS I/O circuits; InP; InP-HBT technology; bipolar devices; circuit topology; clock phase margin; demultiplexing operation; error-free operation; full-rate 4:1 multiplexer; low supply voltage operation; parallel current-switching latch; CMOS technology; Circuit topology; Clocks; Demultiplexing; Heterojunction bipolar transistors; Latches; Low voltage; Multiplexing; Personal communication networks; Power dissipation;
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium, 2004. IEEE
Print_ISBN :
0-7803-8616-7
DOI :
10.1109/CSICS.2004.1392552
