Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic

Author

Nigussie, Ethiopia ; Plosila, Juha ; Isoaho, Jouni

Author_Institution

Dept. of Inf. Technol., Turku Univ.

fYear

2006

fDate

21-24 May 2006

Lastpage

2220

Abstract

In this paper we present the circuit implementation of a new asynchronous on-chip link structure, where two modules placed on the opposite sides of the link can exchange data simultaneously. The link uses a special communication protocol called 2-color 1-phase in which the number of communication actions per transfer is only one, making it potentially faster than the conventional handshake-based protocols. The transceiver circuits are designed using multiple-valued current-mode logic, linear summation is implemented by wiring without active devices simplifying the resulting circuitry. By using 90mV voltage swing the power consumption of the link is 16mW for 178ps propagation delay and 2mm interconnect length. The circuit is designed and simulated using Cadence Analog Spectre with a 0.13mum CMOS technology

Keywords

CMOS integrated circuits; asynchronous circuits; current-mode logic; encoding; integrated circuit interconnections; microprocessor chips; multichip modules; protocols; system-on-chip; transceivers; 0.13 micron; 16 mW; 2-color 1-phase; 90 mV; CMOS technology; Cadence Analog Spectre; asynchronous on-chip link; communication protocol; current-mode logic; dual-rail encoding; full-duplex link; transceiver circuit; CMOS logic circuits; CMOS technology; Encoding; Logic circuits; Logic design; Logic devices; Protocols; Transceivers; Voltage; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693060

Filename

1693060