DocumentCode
2540603
Title
A parallel search algorithm for CLNS addition optimization
Author
Vouzis, Panagiotis D. ; Arnold, Mark G.
Author_Institution
Dept. of Comput. Sci. & Eng., Lehigh Univ., Bethlehem, PA
fYear
2006
fDate
21-24 May 2006
Lastpage
2420
Abstract
We present analytical formulas for the calculation of the memory requirements for a system using the complex logarithmic number system (CLNS). Certain properties of the CLNS addition algorithm allow replacement of a large memory by smaller multiple memories and combinational circuitry. The multiple memories combined with a parallel search algorithm offer memory savings up to 90% at the cost of extra hardware. However, depending on the particular case, there is a tradeoff between memory and combinational logic used
Keywords
combinational circuits; digital arithmetic; parallel memories; search problems; CLNS addition optimization; combinational circuitry; combinational logic; complex logarithmic number system; memory requirements; multiple memories; parallel search algorithm; Circuits; Computer science; Costs; Fast Fourier transforms; Hardware; Logic; Quantization; Read only memory; Signal to noise ratio; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693110
Filename
1693110
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