Mismatch effect analyses in CMOS tapered buffers

A study of delay deviation in CMOS tapered buffers due to transistor mismatching is presented. Theoretical relations for the delay deviation were derived from the buffer and transistor parameters. To validate those relations, and to investigate the buffer behavior, special test structures consisting of tapered buffers configured as ring oscillators were designed in a 0.35 mum CMOS technology. The experimental results are consistent with the proposed relations, and they show that small taper factors produce higher delay deviations. An increase of 23% in the delay standard deviation is observed when the taper factor is reduced from 6 to 2.9