An area-efficient, pulse-based interconnect

We present a new style of long-distance, on-chip interconnects based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most significant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency figures from simulation on a 0.18 mum technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1 mm