Linearity test for high resolution DACs using low-accuracy DDEM flash ADCs

This work proposed a built-in self-test (BIST) strategy for DAC linearity test by utilizing the deterministic dynamic element matching (DDEM) technique in a common flash ADC. DDEM technique allows low-resolution and low-accuracy ADCs work as test devices. In order to provide high resolution/accuracy test abilities, a fine quantization stage and an input dithering DAC are incorporated. In this paper, the architecture of the test system and the test procedure are described. The test performance is analyzed theoretically and verified by numerical simulation. Simulation results show that a two-step flash ADC composed of a 6-bit coarse DDEM stage and a 6-bit fine stage, plus an incorporated 5-bit dithering DAC, with linearity of all the blocks no more than 6 bits, is capable of testing 14-bit DACs