Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers

Author

Mak, Pui-In ; U, Seng-Pan ; Martins, R.P.

Author_Institution

FST, Macau Univ., Macao

fYear

2006

fDate

21-24 May 2006

Abstract

The proliferation of multiple WLANs and the continuous scaling of CMOS have created the need for low-voltage multistandard WLAN receivers. Instead of approaching a complicated SoC, a 3D-stack SiP appears as a promising alternative to meet those requirements in conjunction with the obvious goals of low power and low cost. This paper, focused on the SiP implementation of a WLAN receiver, presents the design and test strategies underlying its analog-baseband portion to accomplish: low-voltage operation; 802.11a/b/g compliance; high routability in 3D stacking; and net-response testability of the functional blocks

Keywords

CMOS analogue integrated circuits; IEEE standards; design for testability; low-power electronics; radio receivers; system-in-package; wireless LAN; 3D-stack SiP; 802.11a; 802.11b; 802.11g; CMOS; WLAN receivers; low-voltage analog-baseband IC; multiple WLAN; net-response testability; Analog integrated circuits; Circuit synthesis; Costs; Frequency synthesizers; Integrated circuit interconnections; Integrated circuit testing; Packaging; Voltage; Wideband; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693124

Filename

1693124