Process tolerant calibration circuit for PLL applications with BIST

A process-invariant calibration circuit, capable of correcting performance errors in charge-pump based PLLs is described. Process variations detrimentally affect all building blocks of standard PLL architectures. Utilizing a novel ADC, these variations are sensed and corrected. The self-calibration circuitry is non-intrusive and requires minimal area and power overhead. A case study of a 2.4GHz ring VCO-based PLL designed in a TSMC´s 0.18mum CMOS mixed-signal technology is given. The calibration circuitry is able to sense and calibrate under all four process corners as well as detect under high temperature conditions