Evolutionary computation in the design of logic circuits

This paper presents two evolutionary schemes and a swarm intelligence algorithm for the design of combinational logic circuits. A genetic and a memetic schemes as the evolutionary algorithms. The particle swarm optimization as the swarm algorithm. The fitness function used in these three algorithms is sequential, that is, divided in two parts. The first part of the fitness function f₁ evaluates the circuit functionality, while the second part f₂ deals with the circuit complexity. The experiments consist in applying the algorithms in the design of two arithmetic circuits: the one-bit full adder and the one-bit full subtracter. We also present a scalability analysis using the parity checker family of circuits.