Direct PWM Synchronization Using An All Digital Phase-Locked Loop for High Power Grid-Interfacing Converters

For medium voltage high power grid-interfacing converters, the operating switching frequency is often around several hundred Hz to reduce the switching power losses. Therefore, to eliminate the even order harmonics and non-characteristic harmonics and to minimize the beat phenomenon, synchronous PWM techniques are desired for the high power low-switching converters. In this paper, a direct PWM synchronization method using an all digital phase-locked loop (ADPLL) is proposed for the grid-connected converter implementation. The control method is realized using a designed DSP-FPGA control system. The proposed ADPLL implemented in the FPGA has wide track-in range and fast pull-in time with an input frequency feed-forward loop. The phase error and pulse jitter is minimized by selecting a high clock frequency (150MHz). The synchronous PWM waveform can be generated effectively and conveniently by the ADPLL through external synchronized interrupt from FPGA to DSP at the desired sampling angle and switching frame starting angle. The proposed ADPLL synchronized PWM strategy has been verified experimentally using a 10kVA grid-connected PWM current source rectifier prototype.