Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip

This paper presents an efficient real time variable block size motion estimation (VBSME) ASIC chip, which represents a step to an H.264/AVC full encoder on chip. The proposed architecture is a SIMD architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using the TSMC 0.18 mum CMOS technology. It processes 31 CIF frames per second with 122 MHz clock frequency. It can operate at frequencies of up to 156 MHz. The prototyped architecture has 3.345 mm² core area including 2372 bytes of SRAMs and it consumes 283.96 mW @ 122MHz