Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip

Author

Sayed, Mohammed ; Amer, Ihab ; Badawy, Wael

Author_Institution

Dept. of Electr. & Comput. Eng., Calgary Univ., Alta.

fYear

2006

fDate

21-24 May 2006

Lastpage

2616

Abstract

This paper presents an efficient real time variable block size motion estimation (VBSME) ASIC chip, which represents a step to an H.264/AVC full encoder on chip. The proposed architecture is a SIMD architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using the TSMC 0.18 mum CMOS technology. It processes 31 CIF frames per second with 122 MHz clock frequency. It can operate at frequencies of up to 156 MHz. The prototyped architecture has 3.345 mm² core area including 2372 bytes of SRAMs and it consumes 283.96 mW @ 122MHz

Keywords

CMOS integrated circuits; SRAM chips; motion estimation; parallel processing; system-on-chip; video coding; 0.18 micron; 122 to 156 MHz; 2372 Bytes; 283.96 mW; AVC encoder; H.264 encoder; SIMD architecture; SRAM; application specific integrated circuits; full encoder on chip; variable block size motion estimation; Application specific integrated circuits; Automatic voltage control; CMOS technology; Computer architecture; Costs; Frequency; MPEG 4 Standard; Motion estimation; Prototypes; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693159

Filename

1693159