Dynamic Equivalent Circuit Design in Three-level High Voltage Inverters Based On Functional Model of IGCT

The integrated gate commutated thyristors (IGCTs) are commonly used for construction of high voltage three-level PWM controlled voltage source converter/inverters. When the output voltage is greater than the maximum rated voltage, IGCTs are connected in series. To ensure the safe and reliable operation of the converter/inverters, special measures are required to equalize the voltages across the IGCTs connected in series. An effective method for balancing voltages is to use resistors for static voltage balancing and RC snubber circuits for dynamic voltage balancing. However, most of the previous research work reported in the literature focused on the dynamic circuit design for converters of the BUCK topology. Trade off is made only between the performance of dynamic voltage balancing and the turn-on loss without any consideration of di/dt endurance and any procedural steps, which makes the design procedure not suitable for converters of the three-level topology. Based on a functional model of IGCTs, this paper presents a procedure for optimum design of the dynamic voltage balancing circuit for a 6 kV/1250 kW inverter. The specific transient processes in the three-level topology with dynamic snubber circuit are simulated and the mechanisms are analyzed, which is absent in the previous work.