Design for test (DFT) for an embedded ARM system on a chip

The design of systems on a chip presents a number of challenges from a design for test (DFT) point of view. The biggest issue is dealing with data transfers across multiple clock domains. To ease layout constraints, these clocks may be regarded as being asynchronous to each other. Low power design means even more clock domains through gated clocks. These designs are often pin-limited as well. Other challenges include the presence of on-chip processors and processor busses, analog block interfaces and embedded memory alongside the digital logic. This paper will present a scheme to analyse and deal with the DFT of multiple clocks and will outline how the other challenges are met in the context of the design of an embedded ARM system on a chip