Low-power 200 Msps, area efficient, 5-tap programmable FIR filter

A two-sample per cycle, programmable 5-tap, area efficient, FIR filter for hard-disk drive PRML read-channels is presented. The design is optimised for low-power, achieving a figure of 6.25 μW/MHz with a gate density of 2.3 K, by a combination of algorithmic, architectural, circuit-level and layout techniques