FPGA based efficient architecture for image watermarking using Wavelet Co-efficients Quantization

In this work, FPGA based pipelined architecture for blind and robust image watermarking algorithm has been presented using Wavelet Co-efficients Quantization. The architecture is designed using new hardware accelerator tool of Xilinx System Generator. The goal of this work is to utilize the option of System Generator for the designing of signal processing algorithm on FPGA and to optimize the design in terms of latency and hardware resources. The latency of the architecture is reduced by exploiting the concurrent execution capability of the device and with reduction in significant areas of the design. In addition, hardware resources are reduced by the use of pipeline registers in the place of input and output buffers that cost no extra hardware. The results demonstrate the successful implementation of the proposed design with the PSNR value of 42dB. The maximum design frequency is 141.9 MHz with watermark embedding delay of 25.2 μsec.