A high speed and energy efficient full adder design using complementary & level restoring carry logic

In this paper, we propose a low complexity full adder design (10-transistor per bit) featuring higher computing speed, lower operating voltage, and lower energy consumption compared with peer designs. The design adopts inverter buffered XOR/XNOR designs to alleviate the threshold voltage loss problem, which often prevents the full adder design from low supply voltage operation and from direct cascading. The proposed design successfully embeds the buffering circuit in the full adder design so as to enhance the speed performance while keeping the transistor count as minimum. For performance comparison, both DC and AC performances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35mum process models, indicate that the proposed design has the lowest working V_dd and highest working frequency among all designs using 10 transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases