A low power 12-bit ADC for systems applications

A low power 12-bit successive approximation ADC is described. A novel coupling capacitor technique is used to relieve the comparator of a large DAC capacitive load. This allows a substantial reduction in overall power consumption. 12-bit linearity is achieved without component trim or calibration. Also the comparator is used with a preset mode to obtain higher speed operation. Digital control logic power is minimised, using in this case a ripple-carry counter. This yielded, on a 0.7 μm CMOS process, a 2 Msps 12-bit accurate analog to digital converter consuming 3.6 mW/MHz from a 3.3 V supply