Hybrid Synchronous/Stationary Reference-Frame-Filtering-Based PLL

Designing an effective phase-locked loop (PLL) for three-phase applications is the objective of this paper. The designed PLL structure is able to provide an accurate estimation of the grid voltage frequency and the phase, even in the presence of all harmonic components of both positive and negative sequences and the dc offset in its input. In addition to offering a high disturbance rejection capability, the suggested PLL structure has a fast transient response and provides a settling time of around two cycles of the fundamental frequency. The effectiveness of the suggested PLL structure is confirmed using numerical results.