Title :
A CMOS monolithic implementation of a nonlinear element for arbitrary 1D map generation
Author :
Yuan, Jie ; Farhat, Nabil ; Van der Spiegel, Jan
Author_Institution :
Dept. of Electr. & Syst. Eng., Pennsylvania Univ., Philadelphia, PA
Abstract :
In a macroscopic approach, a single-chip cortical patch is designed based on the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabricated in a 0.6 mum CMOS process, and is driven under signals with 1 MHz frequency. It covers a die has an area of 0.2 mm2, and consumes 40 mW power, with a 5 V supply
Keywords :
CMOS integrated circuits; bifurcation; integrated circuit design; logic design; monolithic integrated circuits; neural nets; 0.6 micron; 1 MHz; 12 bit; 40 mW; 5 V; CMOS integrated circuit design; CMOS monolithic implementation; arbitrary 1D map generation; bifurcating neuron; nonlinear element; single-chip cortical patch; Bifurcation; Biological system modeling; CMOS process; Design engineering; Fires; Iron; Neurons; Power system modeling; Semiconductor device modeling; Virtual manufacturing;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693197
