DocumentCode
2542878
Title
Hierarchical extraction of critical area for shorts in very large ICs
Author
Nag, Pranab K. ; Maly, Wojciech
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1995
fDate
13-15 Nov 1995
Firstpage
19
Lastpage
27
Abstract
This paper describes an algorithm for efficiently extracting critical area in large VLSI circuits. The algorithm, implemented to handle shorts between electrical nets, takes advantage of the available hierarchy in the layout description in order to speed-up computation and minimize memory usage. The developed software-CREST-was tested for a spectrum of actual IC designs and was found very efficient as compared to existing techniques
Keywords
VLSI; circuit layout CAD; integrated circuit layout; CREST software; IC design; critical area extraction; hierarchical extraction; large VLSI circuits; layout description; shorts; very large ICs; Circuit faults; Circuit testing; Conducting materials; Geometry; Integrated circuit testing; Semiconductor materials; Software testing; Very large scale integration; Virtual manufacturing; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location
Lafayette, LA
ISSN
1550-5774
Print_ISBN
0-8186-7107-6
Type
conf
DOI
10.1109/DFTVS.1995.476933
Filename
476933
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