DocumentCode :
2543061
Title :
Fabrication technique for ultra low leakage embedded DRAM cell transistor
Author :
Iwasaki, Taichi ; Yamamoto, Kenichi ; Sakamoto, Keiji ; Morita, Tomotake ; Tomita, Ryuji ; Morikuni, Hiromi ; Fujishiro, Akihiro ; Nakayama, Tomoo ; Moritoki, Masashige
fYear :
2011
fDate :
9-10 June 2011
Firstpage :
17
Lastpage :
18
Abstract :
DRAM (Dynamic Random Access Memory) cell consists of a transistor and a capacitor, and the capacitor needs to be charged or discharged to achieve the memory function. However, as the technology has been advanced, both cell transistor and a capacitor have been significantly shrunk. So charge leakage has been a crucial issue for present DRAM. To prevent the leakage, commodity DRAM maker chooses non silicide, and low S/D (Source/Drain) doping concentration. On the other hand, as LSI applications expand, high speed DRAM demand has been increasing. So embedded DRAM and silicide applied technology, i.e. leakage control techniques could be a semiconductor manufacturers´ competitiveness today.
Keywords :
DRAM chips; large scale integration; transistors; LSI application; charge leakage control; dynamic random access memory cell; fabrication technique; low S-D doping concentration; semiconductor manufacturer; ultra low leakage embedded DRAM cell transistor; Annealing; Junctions; Logic gates; Probability distribution; Random access memory; Silicides; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Junction Technology (IWJT), 2011 11th International Workshop on
Conference_Location :
Kyoto
Print_ISBN :
978-1-61284-131-1
Type :
conf
DOI :
10.1109/IWJT.2011.5969990
Filename :
5969990
Link To Document :
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