DocumentCode
2543092
Title
Scalable FPGA-based multiprocessor architecture for real-time embedded vision
Author
Samarawickrama, Mahendra ; Rodrigo, Ranga ; Pasqual, Ajith
Author_Institution
Dept. of Electron. & Telecommun. Eng., Univ. of Moratuwa, Moratuwa, Sri Lanka
fYear
2010
fDate
17-19 Dec. 2010
Firstpage
172
Lastpage
176
Abstract
Real-time image processing demands much more processing power than a conventional processor can deliver. As a result hardware acceleration became necessary to augments processors with application-specific coprocessors. Due to the limited resources on FPGA and nature of some sequential algorithms, it is difficult to depend entirely on slice resources. In this research, we implemented a multiprocessor architecture to support real-time image processing on FPGA. Furthermore, we benchmarked and compared our implemented architectures with their counterparts. The operational structure of multiprocessor architecture consists of on-chip processors implemented in a parallel manner with efficient memory and bus architectures. The performance properties such as accuracy, throughput and efficiency are measured and presented. Multiprocessor systems are effective in software level parallelism on FPGA. Our quad-Microblaze architecture achieved 75-80% performance improvement compared to its single Microblaze counterpart. Moreover, the quad-Microblaze design is faster than the single-powerPC implementation on FPFA. Therefore, multi-processor architecture with customised coprocessors are effective for implementing custom parallel architecture to achieve real-time image processing.
Keywords
field programmable gate arrays; image processing; multiprocessing systems; image processing; quad microblaze design; real time embedded vision; scalable FPGA based multiprocessor architecture; single powerPC implementation; software level parallelism; Computer architecture; Field programmable gate arrays; Hardware; Process control; Random access memory; Real time systems; Software; FPGA; Microblaze; PowerPC; cache optimization; memory configuration; multi-processor real-time architecture; mutex;
fLanguage
English
Publisher
ieee
Conference_Titel
Information and Automation for Sustainability (ICIAFs), 2010 5th International Conference on
Conference_Location
Colombo
Print_ISBN
978-1-4244-8549-9
Type
conf
DOI
10.1109/ICIAFS.2010.5715655
Filename
5715655
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